1. Field of the Invention
The present invention relates to a method for processing or treating of semiconductor wafers including insulating isolation trenches for forming integrated semiconductor circuits, in particular directed at a reduction of a bending of the process wafer, thereby avoiding the creation of interfering crystal defects during the further process flow. The product by process without steps within the cap layer is also claimed.
2. Description of Related Art
For the integration of low voltage logic elements and high voltage power elements into the same silicon circuitry it is necessary to insulate chip areas from each other that have different potentials. One approach in this respect is the so-called dielectric trench isolation. In this case a first vertically acting insulation is formed between the device and the substrate by a buried insulating layer (typically comprised of silicon dioxide: SiO2, in principle, any other insulating layers may be used). A further laterally acting (vertical) insulation is established by etching a trench down to the buried insulating layer of an SOI wafer and a subsequent refilling of this deep trench with insulating layers (insulating isolation trench). In this case only a portion or lateral section of the etched trench may be filled with an insulating material, the remaining fill process may then be performed on the basis of at least one conductive fill layer (e.g., polysilicon).
By means of so-called planarization steps, for instance appropriate etch processes or chemical mechanical polishing processes a planarization of the surface may be accomplished.
The representative prior art is found, for example, in EP-A 1 184 902 and EP-A 1 220 312. The process step for forming the insulating isolation trench is in the middle of the process flow, that is, further high temperature process steps follow. During the subsequent further manufacturing process also oxidation steps are required for thermally forming oxide layers. Thereby, an oxidation of the vertical side walls within the insulating isolation trench is induced. With the usual employment of polysilicon as fill layer there is additionally an oxidation of the polysilicon at the surface and also inside the filled insulating isolation trench.
Due to the higher specific volume of the created silicon dioxide compared to the polysilicon, significant compressive stress is generated in portions near the surface of the filled isolation trenches, thereby inducing an expansion of the isolation trenches and a bending of the silicon wafer as well as generation of crystalline defects in the adjacent single crystalline silicon areas, respectively. The crystalline defects impair the characteristics of the devices and result in increased defective goods, respectively. For this reason the trench areas are covered by an oxygen impermeable layer or a corresponding layer system, as is known from U.S. Pat. No. 5,933,746. Such cap layers are also described in U.S. Pat. No. 5,581,110, US-A 2002/0025654, JP-A 2000-183156 and JP-A 63-003429. A disadvantage of such cap layers designed in a known manner is that these layers extend above the planar surface, which entails disadvantages in the further manufacturing process. The layers form a step, which may negatively affect the formation of conductive lines extending across the step, for instance due to a reduced thickness at the line edges. Moreover, the cap layers are defined by an additional photolithographic process and are subsequently etched, that is, a photo mask has to be formed and deposited on the wafer, and there is the risk of a lateral misalignment of the photo mask.